4.3.13.5 Implementation notes

nRF5x devices all look the same and regular. Device at address 0x4000000 has number 0 and interrupt 0, device at address 0x40001000 has number 1 and interrupt 1, and so on.

enum nrf5x_peripheral_id_e defines available peripheral IDs. All of them map to an address range, and an interrupt source to NVIC.

NRF_PERIPHERAL_ADDR and nrf_peripheral_addr allow to retrieve device base address, NRF_STATIC_RES_PERIPHERAL_MEM is a shortcut for declaring a DEV_STATIC_RES_MEM for a device.

Inside a device register map, there are tasks, events, shorts, interrupt handling, and then configuration registers.

This regular pattern explains why nRF5x architecture declaration adds an overlay on top of cpu_mem_read_32 and cpu_mem_write_32 to access hardware registers. nRF5x code use the following accessors:

• nrf_task_trigger,

• nrf_event_check,

• nrf_event_clear,

• nrf_event_wait,

• nrf_event_wait_clear,

• nrf_it_is_enabled,

• nrf_it_set_mask,

• nrf_it_enable,

• nrf_it_enable_mask,

• nrf_it_disable,

• nrf_it_disable_mask,

• nrf_short_set,

• nrf_short_enable,

• nrf_short_enable_mask,

• nrf_short_disable,

• nrf_short_disable_mask,

• nrf_reg_get,

• nrf_reg_set.

All these accessors take device base address and task/event/register number as arguments. These accessors make the code obvious about what the driver intends to do.

PPIs are statically allocated by drivers as needed. This is done through the CONFIG_DRIVER_NRF5X_PPI_ENUM enum config token.

GPIOTE channels are partitioned between GPIO ICU input and PWM outputs. Allocation between those two modules is static.