hexo/ordering.h header reference
[Hardware abstraction layer module]

The source code of this header can be browsed online.

Description  

Serializing operations and memory barrier primitives

Members  

Macros  

Members detail  

#define CPU_ORDER_IO_MEM  

This macro is declared in hexo/ordering.h source file, line 120.

#define CPU_ORDER_IO_READ  

This macro is declared in hexo/ordering.h source file, line 141.

#define CPU_ORDER_IO_WRITE  

This macro is declared in hexo/ordering.h source file, line 130.

#define CPU_ORDER_MEM  

This macro is declared in hexo/ordering.h source file, line 48.

#define CPU_ORDER_READ  

This macro is declared in hexo/ordering.h source file, line 83.

#define CPU_ORDER_READ_WEAK  

This macro is declared in hexo/ordering.h source file, line 102.

#define CPU_ORDER_WRITE  

This macro is declared in hexo/ordering.h source file, line 64.

#define _HEXO_ORDERING_H_  

This macro is declared in hexo/ordering.h source file, line 23.

#define order_compiler_mem()  

This macro is declared in hexo/ordering.h source file, line 44.

this macro is a compiler only memory barrier. Memory accesses are not reordered by the compiler over this barrier. No other guarantee is given.

#define order_io_mem()  

This macro is declared in hexo/ordering.h source file, line 127.

this macro is a compiler and processor read/write memory barrier. Memory accesses are not reordered by the compiler over this barrier and the processor ensure memory accesses do not cross this barrier from platform point of view.

#define order_io_mem_read()  

This macro is declared in hexo/ordering.h source file, line 149.

this macro is a compiler and processor read memory barrier. Memory accesses are not reordered by the compiler over this barrier and the processor ensure all read operations have ended before next read operation starts, from platform and devices point of view.

#define order_io_mem_write()  

This macro is declared in hexo/ordering.h source file, line 138.

this macro is a compiler and processor write memory barrier. Memory accesses are not reordered by the compiler over this barrier and the processor ensure all write operations have ended before next write operation starts, from platform and devices point of view.

#define order_smp_mem()  

This macro is declared in hexo/ordering.h source file, line 57.

this macro is a compiler and processor read/write memory barrier. Memory accesses are not reordered by the compiler over this barrier and the processor ensure memory accesses do not cross this barrier from other processors point of view. This is equivalent to a compiler only barrier for single processor builds.

Alternate declarations with same identifier: [1], [2].

Preprocessor condition: defined( CONFIG_ARCH_SMP )

#define order_smp_mem()  

This macro is declared in hexo/ordering.h source file, line 59.

Documentation from alternate declaration:

this macro is a compiler and processor read/write memory barrier. Memory accesses are not reordered by the compiler over this barrier and the processor ensure memory accesses do not cross this barrier from other processors point of view. This is equivalent to a compiler only barrier for single processor builds.

Alternate declarations with same identifier: [1], [2].

Preprocessor condition: not defined( CONFIG_ARCH_SMP )

#define order_smp_read()  

This macro is declared in hexo/ordering.h source file, line 95.

this macro is a compiler and processor read memory barrier. Memory accesses are not reordered by the compiler over this barrier and the processor ensure all read operations have ended before next read operation starts, from other processors point of view. Should be paired with a write barrier.

This is equivalent to a compiler only barrier for single processor builds.

Alternate declarations with same identifier: [1], [2].

Preprocessor condition: defined( CONFIG_ARCH_SMP )

#define order_smp_read()  

This macro is declared in hexo/ordering.h source file, line 97.

Documentation from alternate declaration:

this macro is a compiler and processor read memory barrier. Memory accesses are not reordered by the compiler over this barrier and the processor ensure all read operations have ended before next read operation starts, from other processors point of view. Should be paired with a write barrier.

This is equivalent to a compiler only barrier for single processor builds.

Alternate declarations with same identifier: [1], [2].

Preprocessor condition: not defined( CONFIG_ARCH_SMP )

#define order_smp_read_weak()  

This macro is declared in hexo/ordering.h source file, line 113.

this macro is a compiler and processor weak read memory barrier. Memory accesses are not reordered by the compiler over this barrier and the processor ensure data dependency between load operations. Should be paired with a write barrier.

This is equivalent to a compiler only barrier for single processor builds.

Alternate declarations with same identifier: [1], [2].

Preprocessor condition: defined( CONFIG_ARCH_SMP )

#define order_smp_read_weak()  

This macro is declared in hexo/ordering.h source file, line 115.

Documentation from alternate declaration:

this macro is a compiler and processor weak read memory barrier. Memory accesses are not reordered by the compiler over this barrier and the processor ensure data dependency between load operations. Should be paired with a write barrier.

This is equivalent to a compiler only barrier for single processor builds.

Alternate declarations with same identifier: [1], [2].

Preprocessor condition: not defined( CONFIG_ARCH_SMP )

#define order_smp_write()  

This macro is declared in hexo/ordering.h source file, line 76.

this macro is a compiler and processor write memory barrier. Memory accesses are not reordered by the compiler over this barrier and the processor ensure all write operations have ended before next write operation starts, from other processors point of view. Should be paired with a (weak) read barrier.

This is equivalent to a compiler only barrier for single processor builds.

Alternate declarations with same identifier: [1], [2].

Preprocessor condition: defined( CONFIG_ARCH_SMP )

#define order_smp_write()  

This macro is declared in hexo/ordering.h source file, line 78.

Documentation from alternate declaration:

this macro is a compiler and processor write memory barrier. Memory accesses are not reordered by the compiler over this barrier and the processor ensure all write operations have ended before next write operation starts, from other processors point of view. Should be paired with a (weak) read barrier.

This is equivalent to a compiler only barrier for single processor builds.

Alternate declarations with same identifier: [1], [2].

Preprocessor condition: not defined( CONFIG_ARCH_SMP )

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