changeset 3957:447032388769

efm32: rtc driver uses EFM32_RTC_ADDR instead of pv->addr
author Alexandre Becoulet <alexandre.becoulet@free.fr>
date Fri, 08 Jun 2018 11:20:18 +0200
parents f7d5c31af3aa
children 9b72e555dfb6
files arch/efm32/drivers/rtc/rtc.c arch/efm32/include/arch/efm32/efm/gecko/devaddr.h arch/efm32/include/arch/efm32/efm/leopard/devaddr.h arch/efm32/include/arch/efm32/efm/zero/devaddr.h
diffstat 4 files changed, 27 insertions(+), 27 deletions(-) [+]
line wrap: on
line diff
--- a/arch/efm32/drivers/rtc/rtc.c	Thu Jun 07 23:58:02 2018 +0200
+++ b/arch/efm32/drivers/rtc/rtc.c	Fri Jun 08 11:20:18 2018 +0200
@@ -38,6 +38,7 @@
 #include <mutek/kroutine.h>
 
 #include <arch/efm32/rtc.h>
+#include <arch/efm32/devaddr.h>
 
 #define EFM32_RTC_HW_WIDTH 24
 #define EFM32_RTC_HW_MASK  0xffffff
@@ -45,8 +46,6 @@
 
 DRIVER_PV(struct efm32_rtc_private_s
 {
-  /* Timer address */
-  uintptr_t addr;
 #ifdef CONFIG_DEVICE_CLOCK
   dev_timer_cfgrev_t rev;
 #endif
@@ -71,19 +70,19 @@
 #ifdef CONFIG_DEVICE_CLOCK_GATING
   dev_clock_sink_gate(&pv->clk_ep, DEV_CLOCK_EP_POWER_CLOCK);
 #endif
-  while (cpu_mem_read_32(pv->addr + EFM32_RTC_SYNCBUSY_ADDR) &
+  while (cpu_mem_read_32(EFM32_RTC_ADDR + EFM32_RTC_SYNCBUSY_ADDR) &
          endian_le32(EFM32_RTC_SYNCBUSY_CTRL))
     ;
-  cpu_mem_write_32(pv->addr + EFM32_RTC_CTRL_ADDR, endian_le32(EFM32_RTC_CTRL_EN(COUNT)));
+  cpu_mem_write_32(EFM32_RTC_ADDR + EFM32_RTC_CTRL_ADDR, endian_le32(EFM32_RTC_CTRL_EN(COUNT)));
 }
 
 /* This function stops the hardware rtc counter. */
 static inline void efm32_rtc_stop_counter(struct efm32_rtc_private_s *pv)
 {
-  while (cpu_mem_read_32(pv->addr + EFM32_RTC_SYNCBUSY_ADDR) &
+  while (cpu_mem_read_32(EFM32_RTC_ADDR + EFM32_RTC_SYNCBUSY_ADDR) &
          endian_le32(EFM32_RTC_SYNCBUSY_CTRL))
     ;
-  cpu_mem_write_32(pv->addr + EFM32_RTC_CTRL_ADDR, 0);
+  cpu_mem_write_32(EFM32_RTC_ADDR + EFM32_RTC_CTRL_ADDR, 0);
 #ifdef CONFIG_DEVICE_CLOCK_GATING
   dev_clock_sink_gate(&pv->clk_ep, DEV_CLOCK_EP_POWER);
 #endif
@@ -95,12 +94,12 @@
    most recent rtc value. */
 static uint64_t get_timer_value(struct efm32_rtc_private_s *pv)
 {
-  uint64_t value = endian_le32(cpu_mem_read_32(pv->addr + EFM32_RTC_CNT_ADDR));
+  uint64_t value = endian_le32(cpu_mem_read_32(EFM32_RTC_ADDR + EFM32_RTC_CNT_ADDR));
 
 #ifdef CONFIG_DEVICE_IRQ
   if (value < EFM32_RTC_HW_MASK / 2)      /* check if a wrap just occured */
     {
-      uint32_t x = endian_le32(cpu_mem_read_32(pv->addr + EFM32_RTC_IF_ADDR));
+      uint32_t x = endian_le32(cpu_mem_read_32(EFM32_RTC_ADDR + EFM32_RTC_IF_ADDR));
       if (x & EFM32_RTC_IF_OF)
         value += 1ULL << EFM32_RTC_HW_WIDTH;
     }
@@ -117,7 +116,7 @@
    channel 0. */
 static inline void efm32_rtc_disable_compare(struct efm32_rtc_private_s *pv)
 {
-  cpu_mem_write_32(pv->addr + EFM32_RTC_IEN_ADDR, endian_le32(EFM32_RTC_IEN_OF));
+  cpu_mem_write_32(EFM32_RTC_ADDR + EFM32_RTC_IEN_ADDR, endian_le32(EFM32_RTC_IEN_OF));
 }
 
 static void efm32_rtc_request_start(struct efm32_rtc_private_s *pv,
@@ -132,18 +131,18 @@
   uint32_t s = 5;
 
   /* enable compare interrupt */
-  cpu_mem_write_32(pv->addr + EFM32_RTC_IEN_ADDR, endian_le32(EFM32_RTC_IEN_COMP0 | EFM32_RTC_IEN_OF));
+  cpu_mem_write_32(EFM32_RTC_ADDR + EFM32_RTC_IEN_ADDR, endian_le32(EFM32_RTC_IEN_COMP0 | EFM32_RTC_IEN_OF));
 
   do {
     /* write deadline in Compare 0 channel */
-    while (cpu_mem_read_32(pv->addr + EFM32_RTC_SYNCBUSY_ADDR) &
+    while (cpu_mem_read_32(EFM32_RTC_ADDR + EFM32_RTC_SYNCBUSY_ADDR) &
            endian_le32(EFM32_RTC_SYNCBUSY_COMP0))
       ;
 
-    cpu_mem_write_32(pv->addr + EFM32_RTC_COMP0_ADDR, endian_le32(d + s));
+    cpu_mem_write_32(EFM32_RTC_ADDR + EFM32_RTC_COMP0_ADDR, endian_le32(d + s));
 
     /* hw compare for == only, check for race condition */
-    uint32_t c = cpu_mem_read_32(pv->addr + EFM32_RTC_CNT_ADDR);
+    uint32_t c = cpu_mem_read_32(EFM32_RTC_ADDR + EFM32_RTC_CNT_ADDR);
 
     if ((d - c /* LE domain write skew */ - 4) & (1 << (EFM32_RTC_HW_WIDTH - 1)))
       {
@@ -160,13 +159,13 @@
  
   lock_spin(&dev->lock);
 
-  uint64_t value = endian_le32(cpu_mem_read_32(pv->addr + EFM32_RTC_CNT_ADDR));
-  uint32_t irq = endian_le32(cpu_mem_read_32(pv->addr + EFM32_RTC_IF_ADDR))
+  uint64_t value = endian_le32(cpu_mem_read_32(EFM32_RTC_ADDR + EFM32_RTC_CNT_ADDR));
+  uint32_t irq = endian_le32(cpu_mem_read_32(EFM32_RTC_ADDR + EFM32_RTC_IF_ADDR))
     & (EFM32_RTC_IF_COMP0 | EFM32_RTC_IF_OF);
 
   if (irq)
     {
-      cpu_mem_write_32(pv->addr + EFM32_RTC_IFC_ADDR, endian_le32(irq));
+      cpu_mem_write_32(EFM32_RTC_ADDR + EFM32_RTC_IFC_ADDR, endian_le32(irq));
 
       if (dev->start_count == 0)
         goto err;
@@ -246,7 +245,7 @@
           if (rqnext != NULL)
             {
               /* start next request, raise irq on race condition */
-              cpu_mem_write_32(pv->addr + EFM32_RTC_IFC_ADDR, endian_le32(EFM32_RTC_IFC_COMP0));
+              cpu_mem_write_32(EFM32_RTC_ADDR + EFM32_RTC_IFC_ADDR, endian_le32(EFM32_RTC_IFC_COMP0));
               efm32_rtc_request_start(pv, rqnext, get_timer_value(pv));
             }
           else
@@ -306,7 +305,7 @@
       /* start request, raise irq on race condition */
       if (dev_request_pqueue_prev(&pv->queue, dev_timer_rq_s_base(rq)) == NULL)
         {
-          cpu_mem_write_32(pv->addr + EFM32_RTC_IFC_ADDR, endian_le32(EFM32_RTC_IFC_COMP0));
+          cpu_mem_write_32(EFM32_RTC_ADDR + EFM32_RTC_IFC_ADDR, endian_le32(EFM32_RTC_IFC_COMP0));
           efm32_rtc_request_start(pv, rq, value);
         }
 
@@ -427,10 +426,9 @@
 {
   struct efm32_rtc_private_s  *pv;
 
-  uintptr_t addr;
-
-  if (device_res_get_uint(dev, DEV_RES_MEM, 0, &addr, NULL))
-    return -ENOENT;
+  __unused__ uintptr_t addr = 0;
+  assert(device_res_get_uint(dev, DEV_RES_MEM, 0, &addr, NULL) == 0 &&
+         EFM32_RTC_ADDR == addr);
 
   pv = mem_alloc(sizeof(struct efm32_rtc_private_s), (mem_scope_sys));
 
@@ -438,7 +436,6 @@
     return -ENOMEM;
 
   memset(pv, 0, sizeof(*pv));
-  pv->addr = addr;
   dev->drv_pv = pv;
 
   /* enable clock */
@@ -466,18 +463,18 @@
 
 #ifdef CONFIG_DEVICE_IRQ
   /* Clear interrupts */
-  cpu_mem_write_32(pv->addr + EFM32_RTC_IFC_ADDR, endian_le32(EFM32_RTC_IFC_MASK));
+  cpu_mem_write_32(EFM32_RTC_ADDR + EFM32_RTC_IFC_ADDR, endian_le32(EFM32_RTC_IFC_MASK));
 
   /* Enable Overflow interrupts */
-  cpu_mem_write_32(pv->addr + EFM32_RTC_IEN_ADDR, endian_le32(EFM32_RTC_IEN_OF));
+  cpu_mem_write_32(EFM32_RTC_ADDR + EFM32_RTC_IEN_ADDR, endian_le32(EFM32_RTC_IEN_OF));
 
   pv->swvalue = 0;
 #else
-  cpu_mem_write_32(pv->addr + EFM32_RTC_IEN_ADDR, 0);
+  cpu_mem_write_32(EFM32_RTC_ADDR + EFM32_RTC_IEN_ADDR, 0);
 #endif
 
   /* Ctrl register configuration */
-  cpu_mem_write_32(pv->addr + EFM32_RTC_CTRL_ADDR, endian_le32(EFM32_RTC_CTRL_DEBUGRUN(FROZEN) |
+  cpu_mem_write_32(EFM32_RTC_ADDR + EFM32_RTC_CTRL_ADDR, endian_le32(EFM32_RTC_CTRL_DEBUGRUN(FROZEN) |
                                                                EFM32_RTC_CTRL_EN(RESET) |
                                                                EFM32_RTC_CTRL_COMP0TOP(TOPMAX)));
 
--- a/arch/efm32/include/arch/efm32/efm/gecko/devaddr.h	Thu Jun 07 23:58:02 2018 +0200
+++ b/arch/efm32/include/arch/efm32/efm/gecko/devaddr.h	Fri Jun 08 11:20:18 2018 +0200
@@ -7,6 +7,7 @@
 #define EFM32_CMU_ADDR 0x400c8000
 #define EFM32_GPIO_ADDR 0x40006000
 #define EFM32_AES_ADDR 0x400e0000
+#define EFM32_RTC_ADDR 0x40080000
 
 #endif
 
--- a/arch/efm32/include/arch/efm32/efm/leopard/devaddr.h	Thu Jun 07 23:58:02 2018 +0200
+++ b/arch/efm32/include/arch/efm32/efm/leopard/devaddr.h	Fri Jun 08 11:20:18 2018 +0200
@@ -8,6 +8,7 @@
 #define EFM32_PRS_ADDR 0x400cc000
 #define EFM32_GPIO_ADDR 0x40006000
 #define EFM32_AES_ADDR 0x400e0000
+#define EFM32_RTC_ADDR 0x40080000
 
 #endif
 
--- a/arch/efm32/include/arch/efm32/efm/zero/devaddr.h	Thu Jun 07 23:58:02 2018 +0200
+++ b/arch/efm32/include/arch/efm32/efm/zero/devaddr.h	Fri Jun 08 11:20:18 2018 +0200
@@ -7,6 +7,7 @@
 #define EFM32_CMU_ADDR 0x400c8000
 #define EFM32_GPIO_ADDR 0x40006000
 #define EFM32_AES_ADDR 0x400e0000
+#define EFM32_RTC_ADDR 0x40080000
 
 #endif