4.3.13.1 Drivers

Clocks [link] 

Clocking in nRF5x is quite simple because most clock dependencies are handled automatically by hardware, and because there are only two clock sources, using fixed frequencies. Nevertheless, clock driver handles many tedious aspects of the clocking of the device:

  • it handles LFCLK calibration when there is no external crystal available,

  • it monitors temperature to see whether to calibrate LFCLK,

  • it tries to delay LFCLK calibration to a later time where HFCLK runs,

  • it handles switching source for LFCLK when requested, and indicates when precision changes,

  • it handles switching source for HFCLK when requested, and indicates when precision changes.

Clock tree is designed to be as straightforward as possible to use. Clock driver exports two clocks:

  • Low Frequency clock, with unspecified precision,

  • High Frequency clock, with unspecified precision.

Clock driver implements two muxes (one for HFCLK, the other for LFCLK). Both can select external crystal or internal RC. If accuracy selected for internal low frequency RC is below 250ppm, calibration is automatically enabled (if CONFIG_DRIVER_NRF5X_CLOCK_LFRC_CAL is selected).

Clock driver also implements throttling. It can be used to dynamically change clock sources and accuracy.

GPIO [link] 

GPIO controller implements both the GPIO class and the ICU class, so that an external peripheral can use a GPIO as an interrupt sink. This feature uses GPIOTE channels in Event mode. .

See also GPIOTE.

PWM [link] 

PWM is a composite device using a timer, PPIs and GPIOTE channels. GPIOTE are used in Task mode. .

See also GPIOTE.

UART [link] 

UART is implemented as a Character Device, fully interrupt driven. Optionnally, nRF UART driver may also be enabled to handle the UART class to support dynamic port reconfiguration.

Printk support is also implemented, it has transparent coexistence support with char/uart device driver on the same hardware block.

Declaration of UART device is board-specific.

I2C [link] 

Hardware I2C block is available with full interrupt support. It only supports master operation, this is a hardware limitation.

SPI [link] 

Hardware SPI-master block is available with full interrupt support.

Slave SPI block is unsupported.

RTC [link] 

RTC is supported as a Timer device. When driver is compiled in, RTC1 instance is declared built-in as "rtc1". RTC0 is left available for BLE radio driver. User may instantiate RTC0 on its own if radio driver is unused.

NVMC [link] 

Flash controller is implemented with two concurrent classes:

  • Memory controller,

Flash access is polled and fully blocking when writing. This is a hardware-enforced requirement.

Timer [link] 

Timers are implemented as Timer devices. When driver is enabled, Timer1 is instantiated as "timer1". Timer0 is left available for BLE radio driver. User may instantiate Timer0 on its own if radio driver is unused.

BLE Radio [link] 

BLE Radio driver implements various network layers, depending on the Bluetooth Low Energy library configuration:

Link-layer (LL demux, Crypto and LLCP) is handled through generic libble network layers.

This driver uses 3 hardware blocks: Radio, RTC0 and Timer0. Timer0 and RTC0 blocks may not be changed to others as there are some hardwired PPIs between them.

Nordic assigns Static Random addresses to its chips. Driver retrieves device address from FICR.

AES [link] 

Hardware AES encrypt block is supported through a crypto driver which supports 4 functions:

  • Basic AES block encrypt,

  • a custom AES-based seedable DRBG,

  • BLE-CCM mode (it only supports CCM operation with BLE-specific parameters),

  • AES-CMAC, a keyed-hash algorithm used in Bluetooth

As most operations are fast and shorter than an interrupt round-trip, cryptographical operations use a delayed queued to handle request from interruptible mode, in a busy-wait manner.

RNG [link] 

Hardware Thermal noise random number generator is supported as a Cryptographic device yielding a random stream without context. Derivation compensation is enabled.

This driver should only be used to seed another RNG.

ADC [link] 

ADC is handled through relevant Valio subclass. Analog pin configuration is done at driver instantiation time.

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